View ISL22319_8328042.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn6310.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) and xdcp are registered trademarks of intersil americas inc. copyright intersil americas inc. 2006, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL22319 single digitally c ontrolled potentiometer (xdcp?) low noise, low power, i 2 c ? bus, 128 taps, wiper only the ISL22319 integrates a si ngle digitally controlled potentiometer (dcp) and non-volatile memory on a monolithic cmos integrated circuit. the digitally controlled potentio meter is implemented with a combination of resistor el ements and cmos switches. the position of the wipers are contro lled by the user through the i 2 c bus interface. the potentiometer has an associated volatile wiper register (wr) and a non-volatile initial value register (ivr) that can be directly written to and read by the user. the contents of the wr controls the position of the wiper. at power up the device recalls the content of the dcp?s ivr to the wr. the dcp can be used as a voltage divider in a wide variety of applications including contro l, parameter adjustments, ac measurement and signal processing. features ? 128 resistor taps ?i 2 c serial interface - two address pins, up to four devices/bus ? non-volatile storag e of wiper position ? wiper resistance: 70 typical @ 3.3v ? shutdown mode ? shutdown current 5a max ? power supply: 2.7v to 5.5v ?50k or 10k total resistance ? high reliability - endurance: 1,000,000 data c hanges per bit per register - register data retention: 50 years @ c ? 8 ld msop ? pb-free (rohs compliant) pinout ISL22319 (8 ld msop) top view 1 2 3 4 8 7 6 5 sda a0 a1 vcc scl gnd shdn rw t+55 ordering information part number (note) part marking resistance option (k ) temp. range (c) package (pb-free) pkg. dwg. # ISL22319ufu8z* 319uz 50 -40 to +125 8 ld msop m8.118 ISL22319wfu8z* 319wz 10 -40 to +125 8 ld msop m8.118 *add ?-tk? suffix for tape and reel. please refe r to tb347 for details on reel specifications. note: these intersil pb-free plastic pack aged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. data sheet september 9, 2009 o b s o l e t e p r o d u c t p o s s i b l e s u b s t i t u t e p r o d u c t i s l 2 2 3 1 6
2 fn6310.1 september 9, 2009 block diagram power-up interface , control and status logic non-volatile registers i 2 c interface v cc gnd rw scl sda a0 a1 wr shdn pin descriptions msop pin symbol description 1 scl open drain i 2 c interface clock input 2 sda open drain serial data i/o for the i 2 c interface 3 a1 device address input for the i 2 c interface 4 a0 device address input for the i 2 c interface 5 gnd device ground pin 6shdn shutdown active low input 7 rw ?wiper? terminal of dcp 8v cc power supply pin ISL22319
3 fn6310.1 september 9, 2009 absolute maximum rati ngs thermal information storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to gnd . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc +0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v voltage at any dcp pin with respect to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup (note 2) . . . . . . . . . . . . . . . . . . class ii, level b @+125c esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kv charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kv thermal resistance (typical, note 1) ja (c/w) 8 lead msop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 maximum junction temperature (plastic package). . . .. . . . .+150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions ambient temperature (extended industrial) . . . . . .-40c to +125c v cc voltage for dcp operation . . . . . . . . . . . . . . . . . . 2.7v to 5.5v wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3ma to 3ma power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mw caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. ????: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. jedec class ii pulse conditions and failure criterion used. level b exceptions are: us ing a max positive pulse of 6.5v on the shdn pin, and using a max negative pulse of -1v for all pins. analog specifications over recommended operat ing conditions unless otherwise stated. symbol parameter test conditions min (note 14) typ (note 3) max (note 14) unit r total end-to-end resistance w option 10 k u option 50 k end-to-end resistance tolerance -20 +20 % end-to-end temperature coefficient w option 50 ppm/c (note 12) u option 80 ppm/c (note 12) r w (note 12) wiper resistance v cc = 3.3v @ +25c, wiper current = v cc /r total 70 c w (note 12) wiper capacitance 25 pf i lkgrw leakage on rw pin voltage at pin from gnd to v cc 24 a voltage divider mode (measured at r w , unloaded) inl (note 8) integral non-linearity -1 1 lsb (note 4) dnl (note 7) differential non-linearity monotonic over all tap positions -0.5 0.5 lsb (note 4) zserror (note 5) zero-scale error w option 0 1 5 lsb (note 4) u option 0 0.5 2 fserror (note 6) full-scale error w option -5 -1 0 lsb (note 4) u option -2 -1 0 tc v (notes 9, 12) ratiometric temperature coefficient dcp register set to 40 hex 4 ppm/c ISL22319
4 fn6310.1 september 9, 2009 operating specifications over the recommended operating condi tions unless otherwise specified. symbol parameter test conditions min (note 14) typ (note 3) max (note 14) unit i cc1 v cc supply current (volatile write/read) 10k dcp, f scl = 400khz; (for i 2 c active, read and write states) 1ma v cc supply current (volatile write/read, non-volatile read) 50k dcp, f scl = 400khz; (for i 2 c active, read and write states) 0.5 ma i cc2 v cc supply current (non-volatile write/read) 10k dcp, f scl = 400khz; (for i 2 c active, read and write states) 3.2 ma v cc supply current (non-volatile write/read) 50k dcp, f scl = 400khz; (for i 2 c active, read and write states) 2.7 ma i sb v cc current (standby) v cc = +5.5v, 10k dcp, i 2 c interface in standby state 850 a v cc = +3.6v, 10k dcp, i 2 c interface in standby state 550 a v cc = +5.5v, 50k dcp, i 2 c interface in standby state 160 a v cc = +3.6v, 50k dcp, i 2 c interface in standby state 100 a i sd v cc current (shutdown) v cc = +5.5v @ +85c, i 2 c interface in standby state 3a v cc = +5.5v @ +125c, i 2 c interface in standby state 5a v cc = +3.6v @ +85c, i 2 c interface in standby state 2a v cc = +3.6v @ +125c, i 2 c interface in standby state 4a i lkgdig leakage current, at pins a0, a1, shdn , sda, and scl voltage at pin from gnd to v cc -1 1 a t dcp (note 12) dcp wiper response time scl falling edge of last bit of dcp data byte to wiper new position 1.5 s t shdnrec (note 12) dcp recall time from shutdown mode from rising edge of shdn signal to wiper stored position and rh connection 1.5 s scl falling edge of last bit of acr data byte to wiper stored position and rh connection 1.5 s vpor power-on recall voltage minimum v cc at which memory recall occurs 2.0 2.6 v v cc ramp v cc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, to dcp initial value register recall completed, and i 2 c interface in standby state 3ms eeprom specification eeprom endurance 1,000,000 cycles eeprom retention temperature c 50 years t wc (note 13) non-volatile write cycle time 12 20 ms t+55 ISL22319
5 fn6310.1 september 9, 2009 serial interface specs v il a1, a0, shdn , sda, and scl input buffer low voltage -0.3 0.3*v cc v v ih a1, a0, shdn , sda, and scl input buffer high voltage 0.7*v cc v cc +0.3 v hysteresis sda and scl input buffer hysteresis 0.05* v cc v v ol sda output buffer low voltage, sinking 4ma 00.4v cpin a1, a0, shdn , sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t sp pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition 1300 ns t low clock low time measured at the 30% of v cc crossing 1300 ns t high clock high time measured at the 70% of v cc crossing 600 ns t su:sta start condition setup time scl rising edge to sda falling edge; both crossing 70% of v cc 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window 0ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc 600 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge; both crossing 70% of v cc 1300 ns t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window 0ns t r sda and scl rise time from 30% to 70% of v cc 20 + 0.1*cb 250 ns t f sda and scl fall time from 70% to 30% of v cc 20 + 0.1*cb 250 ns cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf operating specifications over the recommended operating condi tions unless otherwise specified. (continued) symbol parameter test conditions min (note 14) typ (note 3) max (note 14) unit ISL22319
6 fn6310.1 september 9, 2009 sda vs scl timing rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2k ~2.5k for cb = 40pf, max is about 15k ~20k 1k t su:a a1 and a0 setup time before start condition 600 ns t hd:a a1 and a0 hold time after stop condition 600 ns notes: 3. typical values are for t a = +25c and 3.3v supply voltage. 4. lsb: [v(r w ) 127 ? v(r w ) 0 ]/127. v(r w ) 127 and v(r w ) 0 are v(r w ) for the dcp register set to 7f hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 5. zserror = v(rw) 0 /lsb. 6. fserror = [v(rw) 127 ? v cc ]/lsb. 7. dnl = [v(rw) i ? v(rw) i-1 ]/lsb-1, for i = 1 to 127. i is the dcp register setting. 8. inl = [v(rw) i ? (i ? lsb) ? v(rw) 0 ]/lsb for i = 1 to 127 9. for i = 16 to 127 decimal, t = -40c to +125 c. max() is the maximum value of the wiper voltage and min () is the minimum value of th e wiper voltage over the temperature range. 10. mi = | rw 127 ? rw 0 | /127. mi is a minimum increment. rw 127 and rw 0 are the measured resistances for the dcp register set to 7f hex and 00 hex respectively. 11. roffset = rw 0 /mi, when measuring between rw and rl. roffset = rw 127 /mi, when measuring between rw and rh. 12. this parameter is not 100% tested. 13. t wc is the time from a valid stop condi tion at the end of a write sequence of i 2 c serial interface, to the end of the self-timed internal non-volatile write cycle. 14. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established b y characterization and are not production tested. operating specifications over the recommended operating condi tions unless otherwise specified. (continued) symbol parameter test conditions min (note 14) typ (note 3) max (note 14) unit tc v max v rw () i () min v rw () i () ? max v rw () i () min v rw () i () + [] 2 ? --------------------------------------------------------------------------------------------- - 10 6 +165c -------------------- - = t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t sp t hd:sto ISL22319
7 fn6310.1 september 9, 2009 a0 and a1 pin timing t hd:a scl sda a0, a1 t su:a clk 1 start stop typical performance curves figure 1. wiper resistance vs tap position [i(rw) = v cc /r total ] for 10k (w) figure 2. standby i sb vs v cc figure 3. dnl vs tap position in voltage divider mode for 10k (w) figure 4. inl vs tap position in voltage divider mode for 10k (w) 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 v cc = 3.3v, t = +125oc wiper resisitance (w) tap position (decimal) v cc = 3.3v, t = +20oc v cc = 3.3v, t = -40oc 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.73.23.74.24.75.2 vcc (v) t = +25c isb (a) t = +125c -0.2 -0.1 0 0.1 0.2 0 20406080100120 tap position (decimal) v cc = 2.7v v cc = 5.5v dnl (lsb) t = +25c -0.2 -0.1 0 0.1 0.2 0 20 40 60 80 100 120 tap position (decimal) inl (lsb) t = +25c v cc = 2.7v v cc = 5.5v ISL22319
8 fn6310.1 september 9, 2009 figure 5. zserror vs temperature figure 6. fserror vs temperature figure 7. end-to-end r total % change vs temperature figure 8. tc for voltag e divider mode in ppm figure 9. midscale glitch, code 3fh to 40h figure 10. large signal settling time typical performance curves (continued) -0.30 -0.10 0.10 0.30 0.50 0.70 0.90 1.10 1.30 -40 -20 0 20 40 60 80 100 120 temperature (oc) zserror (lsb) 10k v cc = 5.5v v cc = 2.7v 50k -1.50 -1.20 -0.90 -0.60 -0.30 0.00 -40-20 0 20406080100120 temperature (oc) fserror (lsb) 50k v cc = 2.7v 10k vcc = 5.5v -1.0 -0.5 0.0 0.5 1.0 -40-20 0 20406080100120 temperature (oc) end-to-end r total change (%) v cc = 5.5v v cc = 2.7v 50k 10k 0 15 30 45 60 75 90 105 16 36 56 76 96 tap position (decimal) tcv (ppm/c) 10k 50k signal at wiper (wiper unloaded signal at wiper (wiper unloaded movement from 7fh to 00h) ISL22319
9 fn6310.1 september 9, 2009 pin description potentiometers pins rw rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the wr register. shdn the active low shdn pin forces the resistor to end-to-end open circuit condition and shorts rwi to gnd. when shdn is returned to logic high, the previous latch settings put rw at the same resistance setting prior to shutdown. this pin is logically anded with shdn bit in acr register. i 2 c interface is still available in shutdown mode and all registers are accessible. this pin must remain high for normal operation (see figure 11). bus interface pins serial data input/output (sda) the sda is a bidirectional serial data input/output pin for i 2 c interface. it receives device address, operation code, wiper address and data from an i 2 c external master device at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock. sda requires an external pull-up resistor, since it is an open drain input/output. serial clock (scl) this is the serial clock input of the i 2 c serial interface. scl requires an external pull-up resistor, since it is an open drain input. device address (a1, a0) the address inputs are used to set the least significant 2 bits of the 7-bit i 2 c interface slave address. a match in the slave address serial data stream must match with the address input pins in order to initiate communication with the ISL22319. a maximum of 4 ISL22319 devices may occupy the i 2 c serial bus. principles of operation the ISL22319 is an integrated circuit incorporating one dcp with its associated registers, non-volatile memory and an i 2 c serial interface providing direct communication between a host and the potentiometer and memory. the resistor array is comprised of individual resistors connected in series. at either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on the device operate in a ?make before break? mode when the wiper changes tap positions. when the device is powered down, the last value stored in ivr will be maintained in the non-volatile memory. when power is restored, the contents of the ivr is recalled and loaded into the wr to set the wiper to the initial value. dcp description the dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fi xed terminals of a mechanical potentiometer and internally connected to v cc and gnd. the rw pin of the dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by an 7-bit volatile wiper register (wr). when the wr of a dcp contains all zeroes (wr[6:0]= 00h), its wiper terminal (rw) is closest to gnd. when the wr register of a dcp contains all ones (wr[6:0] = 7fh), its wiper terminal (rw) is closest to v cc . as the value of the wr increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to gnd to the closest to v cc . while the ISL22319 is being powered up, the wr is reset to 40h (64 decimal), which locates rw roughly at the center between v cc and gnd. after the power supply voltage becomes large enough for reliable non-volatile memory reading, the wr will be reload with the value stored in a non-volatile initial value register (ivr). the wr and ivr can be read or written to directly using the i 2 c serial interface as described in the following sections. memory description the ISL22319 contains one non-volatile 8-bit register, known as the initial value register (ivr), and two volatile 8-bit registers, wiper register (wr) and access control register (acr). the memory map of ISL22319 is on table 1. the non-volatile register (ivr) at address 0, cont ains initial wiper position and volatile register (wr) contains current wiper position. the non-volatile ivr and volatile wr registers are accessible with the same address. rw figure 11. dcp connection in shutdown mode table 1. memory map address non-volatile volatile 2? acr 1reserved 0ivr wr ISL22319
10 fn6310.1 september 9, 2009 the access control register (acr) contains information and control bits described below in table 2. the vol bit (acr[7]) determines whether the access is to wiper registers wr or initial value registers ivr. if vol bit is 0, the non-volatile ivr register is accessible. if vol bit is 1, only the volatile wr is accessible. note, value is written to ivr register al so is written to the wr. the default value of this bit is 0. the shdn bit (acr[6]) disables or enables shutdown mode. this bit is logically anded with shdn pin. when this bit is 0, dcp is in shutdown mode. default value of shdn bit is 1. the wip bit (acr[5]) is read only bit. it indicates that non-volatile write operation is in progress. it is impossible to write to the wr or acr while wip bit is 1. shutdown mode the device can be put in shutdown mode either by pulling the shdn pin to gnd or setting the sh dn bit in the acr register to 0. the truth table for shutdown mode is in table 3. i 2 c serial interface the ISL22319 supports an i 2 c bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlli ng the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operatio ns. therefore, the ISL22319 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line must change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 12). on power-up of the ISL22319 the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the ISL22319 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 12). a start condition is ignored during the power-up of the device. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 12). a stop condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. an ack, acknowledge, is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 13). the ISL22319 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful rece ipt of an address byte. the ISL22319 also responds with an ack after receiving a data byte of a write operation. th e master must respond with an ack after receiving a data byte of a read operation a valid identification byte contai ns 01010 as the five msbs, and the following two bits matching the logic values present at pins a1 and a0. the lsb is the read/write bit. its value is ?1? for a read operation, and ?0? for a write operation (see table 4). table 4. identification byte format table 2. access control register (acr) vol shdn wip 00000 table 3. shdn pin shdn bit mode high 1 normal operation low 1 shutdown high 0 shutdown low 0 shutdown 01010a1a0r/w (msb) (lsb) logic values at pins a1 and a0 respectively sda scl start data data stop stable change data stable figure 12. valid data changes, start, and stop conditions ISL22319
11 fn6310.1 september 9, 2009 write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the ISL22319 responds with an ack. at this time, the device enters its standby state (see figure 14). the non-volatile write cycle starts after stop condition is determined and it requires up to 20ms delay for the next non-volatile write. read operation a read operation consists of a three byte instruction followed by one or more data bytes (see figure15). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start, and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the ISL22319 responds with an ack. then the ISL22319 transmits data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a ack and stop condition) following the last bit of the last data byte (see figure15). in order to read back the non-volatile ivr, it is recommended that the application reads the a cr first to verify the wip bit is 0. if the wip bit (acr[5]) is not 0, the host should repeat its reading sequence again. applications information the typical application diagram is shown on figure 16. for proper operation adding 0.1f decoupling ceramic capacitor to v cc is recommended . the capacitor value may vary based on expected noise frequency of the design. sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 13. acknowledge response from receiver s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the slave a c k 00 0 11 a c k write signal at sda 0000 a0 a1 0 figure 14. byte write sequence 0 signals from the master signals from the slave signal at sda s t a r t identification byte with r/w =0 address byte a c k a c k 00 0 11 s t o p a c k 1 identification byte with r/w =1 a c k s t a r t last read data byte first read data byte a c k 0 000 a0 a1 a0 a1 figure 15. read sequence a c k 0 0 010 1 ISL22319
12 fn6310.1 september 9, 2009 v cc v cc v cc r1 r2 0.1f ISL22319 scl rw 0.1f shdn rpu figure 16. typical application diagram for implementing adjustable voltage referance v out sda rpu a0 a1 v cc ISL22319
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6310.1 september 9, 2009 ISL22319 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millim eter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 05 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 2 01/03

▲Up To Search▲

Price & Availability of ISL22319

	To Download ISL22319 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .